AdTEC | CPLD – CY7C375i-83GMB Chip
350424
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CPLD – CY7C375i-83GMB Chip

  • 10ns pin-to-pin logic delays on all the pins.
  • Up to 111 MHz.
  • 216 macrocells with 4,800 usable gates.
  • 128 user I/O pins.
  • 5V In-system programmable
  • Endurance of 10,000 program/erase cycles
  • Program/erase over full industrial voltage and temperature range
  • Enhanced pin-locking architecture
  • Extensive IEEE Std 1149.1 boundary-scan (JTAG) support
  • High-drive 24 mA outputs
  • Advanced CMOS 5V FastFLASH™ technology
  • Available 160-pin PGA package