The main features of RIF board are:
- Sensitivity Time Control (STC):
This feature reduces the impact of returns from sea state. It reduces the minimum SNR of the receiver for a short duration immediately after each pulse is transmitted. The effect of adjusting the STC is to reduce the clutter on the display in the region directly around the transmitter. The greater the value of STC, the greater the range from the transmitter in which clutter will be removed.
- Fast Time Constant (FTC):
FTC is a differentiator, meaning it determines the rate of change in the signal, which it then uses to discriminate pulses which are not changing rapidly. With FTC in operation, only the leading edge of an echo of a long-time duration is displayed on the radarscope. FTC tends to reduce saturation of the scope by clutter.
- Selection of any one of the two Radar Sources
- Selection of any one of the two IFF Videos
- Selected Signal, filtered for noise rejection and delivered to the out put Port after suitable signal processing
- Equipped several link for Command for Reselection
- Gain and Offset adjustment of Each Channel
- Interference Suppression by Sweep-to-Sweep Correlation
- Sensitivity Timing Control (STC) and Fast Time Control (FTC) on Selected Radar Video
- Video type LIN/Log/MTI
This VME based slave card capable of Interfacing to two External Primary Radar Sources and two External Secondary IFF Sources.
Primary Analog video inputs (LIN/LOG/MTI) from the two radar sources shall be adjusted for offset and gain using front panel potentiometers. Then one of the two primary radar sources shall be selected. From the selected radar source the final output shall be one among the three types of videos (LIN//LOG/MTI). There shall be a provision to select Simulated Primary Video also. The final selected video shall be again subjected to software programmable gain and offset adjustment under the control of Host. Then the video shall be either passed various stages of processing such as STC, FTC and IS, before being sent out on the front panel connector.
Secondary Analog Video inputs (IFF) from two radar sources shall be adjusted for gain and offset using front panel potentiometers. Then one among the two shall be selected. There shall be a provision to select Simulated Secondary Video also. Then the selected secondary video shall be again subjected to software programmable gain adjustment under the control of Host. Finally the selected video shall be sent out on Front Panel connector.
Digital inputs from the primary radar sources, namely ACP, SHM, SYNC and EOR shall be conditioned by means of protection, pulse discrimination and validation. There shall be a provision to select Single ended or Differential Inputs. Finally the conditioned digital outputs shall be sent out on Front Panel connector. Control and software programmability by the host is through VME interface, since this card would be used in a VME back plane in combination with other associated cards.
Control and software programmability can also be done using serial port under on-board micro-controller host.
The RIF Board is mainly used in Radar Systems for communicating two signals. The board has two channels namely channel 1 and channel 2 for communicating signals with the radar.
On-board features include 1 Megabit (128 K x 8-Bit) Uniform Sector Flash Memory, 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) Boot Sector Flash Memory, 1-Mbit (64K x 16) Static RAM, High performance Spartan-IIE Xilinx FPGA which has densities ranging from 71,000 to 2,00,000 system gates and System performance is supported beyond 200 MHz, In-System Programmable Configuration PROMs, High performance CPLD which has 288 macro cells with 6,400 usable gates and system frequency up to 208 MHz, Dual 2-input NAND Gate, 12-bit 65MSPS ADC, 1K (128×8) SPI Serial EEPROM.
The RIF board has On-board High-Performance, 80C186-Compatible 16-Bit Embedded USB Microcontroller which has Universal Serial Bus (USB) peripheral controller, High-Speed UART with auto baud, Synchronous serial interface (SSI), Three programmable 16-bit timers, Hardware watchdog timer, Programmable I/O (48 PIO signals), Integrated DRAM controller, Glue less interface to RAM/ROM/Flash memory, Multiplexed and non multiplexed address/data bus, External bus mastering support.