AdTEC | RADAR VIDEO INTERFACE BOARD
350527
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RADAR VIDEO INTERFACE BOARD

  • Built In Test Signal
  • Video Loop back Test
  • Selection of any two Radar Videos
  • Selection of any two IFFr Videos
  • Selected Signal Filtered for noise rejection and offer Suitable signal processing delivered to the out put Port
  • Equipped Several link for Command for Reselection
  • Each Channel Gain and Offset adjustment
  • Video type LIN/Log/MTI

This VME based slave card capable of Interfacing to two External Primary Radar Sources and two External Secondary IFF Sources.

 
Primary Analog:

Primary Analog video inputs (LIN/LOG/MTI) from the two radar sources shall be adjusted for gain and offset using front panel potentiometers. Then the Primary Video signals shall be scaled down to and given out on VME-P2 connector to the next card in the system.

 
Secondary Analog:

Secondary Analog Video inputs (IFF) from two radar sources shall be adjusted for gain and offset using front panel potentiometers. Then the Secondary Video signals shall be scaled down to and given out on VME-P2 connector to the next card in the system.

Digital inputs:

Digital inputs from the primary radar sources, namely ACP, SHM and SYNC shall be conditioned by means of protection, pulse discrimination and validation. Then the buffered Digital signals shall be passed out VME-P2 connector.

 

Video signals and Digital signals shall be fed back to the card after being routed in another associated card of the system. The card shall conduct POST by comparing the looped back signals and the input signals. The card shall also conduct on-line diagnostics by comparing the looped back signals and input signals. Hence, the Card operates in three modes: POST, Normal and On-Line Diagnostic.

 

Control and software programmability by the host is through VME interface, since this card would be used in a VME back plane in combination with other associated cards.

 

The RVIF Board is mainly used in Radar Systems for communicating two signals. The board has two channels namely channel 1 and channel 2 for communicating signals with the radar.

 

On-board features include 1 Megabit (128 K x 8-Bit) Uniform Sector Flash memory, 1K (128×8) SPI Serial EEPROM, In-System Programmable Configuration PROM, High performance Spartan-IIE Xilinx FPGA which has densities ranging from 71,000 to 2,00,000 system gates and System performance is supported beyond 200 MHz, High performance CPLD which has 288 macro cells with 6,400 usable gates and system frequency up to 208 MHz.