AdTEC | SL55x
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Programmable heterogeneous ASSPs based on SIMD/VLIW architecture and flexible hardware engines

Signal Processing Cluster

  1. Highly optimized Signal Conditioning Accelerators
  2. Programmable SPROC ASSPs for flexibility


Forward Error Correction (FEC) Cluster

  1. Decoding of most popular convolutional & algebraic codes
  2. Hardware engines support optimized LDPC decode and multi-standard encode

Dynamic and re-configurable power control loop è Enables intelligent Power Performance tradeoff

  1. Gather signal statistics ( SNR , Dynamic Range, Modulation type and Channel Impulse           Response)
  2. Re-configure the finite bit-width/precision dynamically
  3. Re-configure number of taps based on incoming Noise floor of signal
  4. Dynamic Bit-width control reduces power dissipation without sacrificing performance